Why is opcode is 6 bit long in MIPS 32 bit architecture?

Below is Data transfer instruction format for 32-bit ARM and MIPS architecture. 32-bit ARM architecture have 4 bit opcode because there are 16 registers (2^4=16).32-bit MIPS architecture have 6 bit opcode. Should not it be 5 bits considering there are 32 registers in MIPS?
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