Why is 8086 a 16-bit microprocessor?

It had 16-bit registers and data paths. It could do 16-bit operations as fast 8-bit ones. For example both ADD AX,BX and ADD AL,BL were three cycles (excluding fetching). Z80 was an 8-bit processor that had a similar register set (as they both were derivatives of 8080). In it 8-bit addition like ADD A,B took 4 time states when a 16-bit addition like ADD HL,BC took 11 time states.

Yes, 8086 is a 16-bit Microprocessor. It was designed by Intel between early 1976 to June 8, 1978, when it was released.

We don’t really use the 8086 CPU that much anymore, certainly not in new PCs, what we do continue to use is 8086 instruction set compatibility. (It’s usually referred to as x86 architecture, in reference to 80286, 80386 and 80486 chips that followed the 8086. Use continued through the Pentium and Celeron lines, and continues to this day in Core processors.) What it means is, all op codes and registers supported by the 8086 are still valid on/understood by brand new 8th generation Core i7 CPUs.

The reason we still use this is the absolutely ginormous amount of software written for it, that’s cur

We don’t really use the 8086 CPU that much anymore, certainly not in new PCs, what we do continue to use is 8086 instruction set compatibility. (It’s usually referred to as x86 architecture, in reference to 80286, 80386 and 80486 chips that followed the 8086. Use continued through the Pentium and Celeron lines, and continues to this day in Core processors.) What it means is, all op codes and registers supported by the 8086 are still valid on/understood by brand new 8th generation Core i7 CPUs.

The reason we still use this is the absolutely ginormous amount of software written for it, that’s currently in existence. Of course not all of it still runs on new PCs, code with dependencies on obsolete devices (e.g., floppy diskette drives) or operating system/file system internals (e.g., FAT decoders) go the way of things they depend on. But when you step back and look at the big picture, the depth of down-level compatibility, across nearly four decades of development, is quite phenomenal.

The value of being able to run older software on new chips has been huge, it decouples hardware upgrades from software upgrades, making it possible for business processes to remain intact when systems are replaced. It has come at a price though, everything is a trade-off.

I haven’t seen it written in so many words, but I’m pretty sure the meltdown CPU bug ties directly to x86 register extensions. For example, the AX [16 bit] register on the 8086 became the EAX [32 bit] register on the 80286. Old code that referenced AX got the low-order 16 bits of EAX . On x64 chips it became RAX and EAX became a reference to the low-order 32 bits of RAX.

Even the 8086 had down-level throw-backs to earlier chips, the high-order and low-order 8 bits (aka, nibbles) of AX were called AH and AL, respectively. I suspect that continued support for those nibbles directly contributed to the manifestation of that bug.

Anyways, in a nutshell, the answer to the question why is compatibility, making the most out of our collective investment into software, while at the same time enjoying performance advantages of newer and faster hardware.

The original CPU in the Intel x86 line that continues to this day, and which powers most non-mobile computing devices. It was introduced in 1978 after two years of development.

Based in part on the highly successful 8-bit Intel 8080 microprocessor, the 8086 was a competitive response to Zilog’s 8080 clone, the legendary Z-80. Intel had earlier introduced a CPU called the 8085, which was an improved 8080, but still not as good as a Z-80. The 8086 introduced a new instruction set, but code for an 8080, 8085 or Z-80 could easily be ported to the 8086. The most important new feature of the 8086 was

The original CPU in the Intel x86 line that continues to this day, and which powers most non-mobile computing devices. It was introduced in 1978 after two years of development.

Based in part on the highly successful 8-bit Intel 8080 microprocessor, the 8086 was a competitive response to Zilog’s 8080 clone, the legendary Z-80. Intel had earlier introduced a CPU called the 8085, which was an improved 8080, but still not as good as a Z-80. The 8086 introduced a new instruction set, but code for an 8080, 8085 or Z-80 could easily be ported to the 8086. The most important new feature of the 8086 was its 16-bit internal registers, which allowed it to address a full 1 MB of RAM. Its 8-bit predecessors could address just 64 KB.

Although it was a technological breakthrough, with its 16–bit capability and easy portability from older designs, it didn’t sell well at first. Because of the 16-bit design, the 8086 needed 16-bit core logic, which we call a chipset today. But in those days, it really was a chipset—integration of the support circuitry into just a few chips was not possible with the technology of 40 years ago. And developing and making 16–bit core logic for such a small market was prohibitively expensive. And because the 8086 wasn’t selling, the market for 16-bit software wasn’t developing, either.

Intel responded to this by creating a cut-down version of the 8086, which reduced the width of the data bus from 16 bits to 8, and released it in 1979. This version was exactly the same internally, but because of the change in the data bus, it could run on the same existing 8-bit core logic that the 8080/8085 and Z-80 could. And because it was still 16 bits internally, it could still address 1 MB of RAM and run 16-bit software, just not quite as fast. The 8088 found a market that the 8086 had not.

When IBM chose the 8088 to be the CPU in its new IBM PC in 1981, the rest was history. Intel released a better full 16-bit design, the 80286, in 1982, and then the 32-bit 80386 in 1985 (although it was designed much earlier). AMD expanded the x86 design to 64 bits with the introduction of the Athlon 64 in 2003.

On 5 June 2018, the 40th anniversary of the release of the 8086, Intel announce the Core i7–8086K, a limited edition part honoring its predecessor: Happy Birthday, 8086: Limited-Edition 8th Gen Intel Core i7-8086K Delivers Top Gaming Experience | Intel Newsroom.

Code written for an 8086 can still be executed on modern x86–64 CPU’s.

This question is a bit like asking, “What determines that a vehicle’s engine is 4, 6, or 8 cylinder?” The short answer is that the manufacturer determines whether a microprocessor is 8, 16, 32, or 64 bit. Even today, some manufacturers produce microprocessors (and/or microcontrollers) with a variety of bit sizes, including 8-bit products.

In general, an N-bit microprocessor (CPU) has an ALU (Arithmetic Logic Unit), registers, an address bus, or data bus having N bits. Notice that I said or. This is a pretty broad definition, because some CPU architectures have a mixture of internal sizes and mi

This question is a bit like asking, “What determines that a vehicle’s engine is 4, 6, or 8 cylinder?” The short answer is that the manufacturer determines whether a microprocessor is 8, 16, 32, or 64 bit. Even today, some manufacturers produce microprocessors (and/or microcontrollers) with a variety of bit sizes, including 8-bit products.

In general, an N-bit microprocessor (CPU) has an ALU (Arithmetic Logic Unit), registers, an address bus, or data bus having N bits. Notice that I said or. This is a pretty broad definition, because some CPU architectures have a mixture of internal sizes and might use different sizes internally and externally. The size of the data bus has often been used to drive the bitness of the CPU, but that’s not always the case.

Consider the following examples:

  • Zilog Z80 - Considered an 8-bit CPU, it has an 8-bit data bus, 16-bit address bus, and a mix of 8-bit and 16-bit registers.
  • Intel 8086 - Considered a 16-bit CPU, it has a 16-bit data bus, a 20-bit address bus, and 16-bit registers.
  • Intel 8088 - Considered a 16-bit CPU, even though it has only an 8-bit external data bus. Everything else is identical to the 8086. The original IBM PC was based on this CPU.
  • Intel 80386 - Considered a 32-bit CPU, it has a 32-bit data bus, 32-bit address bus, and 32-bit registers.
  • Intel 80386SX - Considered a 32-bit CPU, even though it has only a 16-bit external data bus and a 24-bit external address bus. Everything else is identical to the 80386.

As you can see, the bitness of a CPU is not always based on the size of the external data bus, the size of the external address bus, or the size of the largest registers. It usually has to do with how much data it can move around at a time internally, but that’s not always the case.

The reality is that 8086 doesn’t have a standard flat memory map. It’s broken down into segments.

The 8086 has a 20bit physical address space , going from 0x00000 to 0xFFFFF. But the processor itself is only 16 bits wide : it’s registers are 16 bits as well as the ALU. The processor simply can’t handle dealing with 20 bit addresses.

The solution to this is actually quite similar to banking ( a technique used to increase memory on older 8 bit system).

Segments are 64KB in size (maximum). Each segment register contains the base address of the segment it’s keeping track of , with the segment offset

The reality is that 8086 doesn’t have a standard flat memory map. It’s broken down into segments.

The 8086 has a 20bit physical address space , going from 0x00000 to 0xFFFFF. But the processor itself is only 16 bits wide : it’s registers are 16 bits as well as the ALU. The processor simply can’t handle dealing with 20 bit addresses.

The solution to this is actually quite similar to banking ( a technique used to increase memory on older 8 bit system).

Segments are 64KB in size (maximum). Each segment register contains the base address of the segment it’s keeping track of , with the segment offset (the Instruction pointer) pointing to a specific location within that segment.

As mentioned , the segment registers are 16bits. This means that if you were to have a segment base address at physical address 0xAFFF0 for example , you simply wouldn’t be able to keep that address in a register : you have to cut it down to 16 bits (4 hex digits), meaning we can only store 0xAFFF in the segment register.

If you remember back in primary school , you were probably though that multiplying by 10 is equivalent to adding a 0 at the end of your number; essentially an arithmetic left shift operation.

It works the same in other number systems as well : multiplying a binary number by 2 is the same as performing a left shift. Multiplying by 16 is the same as 4 left shifts ( or 1 left shift for hexadecimal values).

Effectively , by multiplying by 16 , we took our previously cut down value (0xAFFF) and shifted it to get the number 0xAFFF0, which is exactly the address of our segment. We can then add the offset value to this address giving us the real 20 bit physical address.

Do note that by shifting our address like this , we effectively got rid of the 4 least significant digits. Given that these are addresses , this means that all segments must be aligned on 16 byte boundaries.

https://www.desktopclass.com/computer-it/discuss-different-address-segment-registers.html

There is a notation we follow.
Physical Address
The 20 bit address which needs to be
stored.
It ranges from 00000H to FFFFFH (Hexadecimal notation) .
Base Address:
The address at which a given memory segment starts and we use it for de-markation.
Offset address
(Distance from the base address) is a location with 64 kb segment range. It ranges from 0000H to FFFFH
Logical address
Something we denote on paper as a short hand representation of the above addresses. It consists of a segment value and offset address.
Logical address is specified as
Segment base : Offset value.

Physical address

There is a notation we follow.
Physical Address
The 20 bit address which needs to be
stored.
It ranges from 00000H to FFFFFH (Hexadecimal notation) .
Base Address:
The address at which a given memory segment starts and we use it for de-markation.
Offset address
(Distance from the base address) is a location with 64 kb segment range. It ranges from 0000H to FFFFH
Logical address
Something we denote on paper as a short hand representation of the above addresses. It consists of a segment value and offset address.
Logical address is specified as
Segment base : Offset value.

Physical address is obtained by shifting the segment address 4 bits to left adding the offset address.
ie.,
Physical address = ( Segment base*10H ) + Offset Value.

Ex: If we want to find the physical address of a given
Logical address: A4FBH:4872H
Segment's base address: A4FBH
Offset value: 4872H
Shifting the segment address 4 bits to left A4FBH<<4 gives A4FB0H
Now adding offset address to A4FB0H
We get:

A4FB0H
+
4872H
_____
A9822H
_____

A simplification is that it implies that it has 16 bit arithmetic instructions. 8 bit processors only had 8 bit arithmetic instructions. Modern CPUs have 64 bit arithmetic instructions.

8 bits was always limiting. 16 bits was a bit limiting too, because that only allows for integers between -32768 and 32767. 32 bit was pretty good, but as files got very large, it became a problem because of file size limitations, RAM limitations, and some other limitations.

64 bits seems to be large enough for all uses I know of - if you need larger than 64 bit integers, there’s way around that using arbitrary p

A simplification is that it implies that it has 16 bit arithmetic instructions. 8 bit processors only had 8 bit arithmetic instructions. Modern CPUs have 64 bit arithmetic instructions.

8 bits was always limiting. 16 bits was a bit limiting too, because that only allows for integers between -32768 and 32767. 32 bit was pretty good, but as files got very large, it became a problem because of file size limitations, RAM limitations, and some other limitations.

64 bits seems to be large enough for all uses I know of - if you need larger than 64 bit integers, there’s way around that using arbitrary precision libraries, or simply using floating point values, and accepting a loss of precision. But for addressing memory, 64 bits is more than enough, because that’s a currently inconceivable amount of RAM ( 1.8 * 10^19 bytes of addressable RAM.) And it’s big enough for any files I know of 1000 Petabytes or something like that. While I can conceive of some large database maybe containing that much info, it would not be a single file. But I digress…

Wikipedia says that 64 bits refers to register size and address size. Registers are used by the CPU for computations, intermediate values, and other things. This is also a good answer, but in my experience is the same as the answer in the first sentence ( as register size usually dictates max integer size for arithmetic.)

If this is a homework question, I suggest you use the answer from the course’s text. But if you are asking out of curiosity, I think you will find my simplified answer is pretty accurate.

Thanx for A2A.

Microprocessors do their calculations based on the clock (crystal oscillator) attached externally to the microprocessor. 8086 has internal divide by 3 counter for frequency reduction so as to enable the processor to optimize the timing and to sync with the external peripherals attached.

As far as duty cycle is considered, Duty Cycle is the ratio of "ON Time (High pulse)" and "Total Time (Clock period)" of one cycle. 33% duty cycle implies that the clock pulse is held high for 33% time of the pulse. The 8086 microprocessor operates at 5 MHz frequency. So 1 Clock pulse = 200 nanosec

Thanx for A2A.

Microprocessors do their calculations based on the clock (crystal oscillator) attached externally to the microprocessor. 8086 has internal divide by 3 counter for frequency reduction so as to enable the processor to optimize the timing and to sync with the external peripherals attached.

As far as duty cycle is considered, Duty Cycle is the ratio of "ON Time (High pulse)" and "Total Time (Clock period)" of one cycle. 33% duty cycle implies that the clock pulse is held high for 33% time of the pulse. The 8086 microprocessor operates at 5 MHz frequency. So 1 Clock pulse = 200 nanoseconds. So the microprocessor needs 33% of 200 nanoseconds, that is, 66 nanoseconds high pulse and 134 nanoseconds low going signal.

The above figure might give you a little clearer idea how a 33% Duty cycle looks.

That's the reason we use 15MHz external crystal to the microprocessor. Internal Divide-by-3 we make the duty cycle 33%.

The only available OS at that time was 8 bits 😳.

Pin diagram of 8086 microprocessor is as given below:

Intel 8086 is a 16-bit HMOS microprocessor. It is available in 40 pin DIP chip. It uses a 5V DC supply for its operation. The 8086 uses 20-line address bus. It has a 16-line data bus. The 20 lines of the address bus operate in multiplexed mode. The 16-low order address bus lines have been multiplexed with data and 4 high-order address bus lines have been multiplexed with status signals.

AD0-AD15 : Address/Data bus. These are low order address bus. They are multiplexed with data. When AD lines a

The only available OS at that time was 8 bits 😳.

Pin diagram of 8086 microprocessor is as given below:

Intel 8086 is a 16-bit HMOS microprocessor. It is available in 40 pin DIP chip. It uses a 5V DC supply for its operation. The 8086 uses 20-line address bus. It has a 16-line data bus. The 20 lines of the address bus operate in multiplexed mode. The 16-low order address bus lines have been multiplexed with data and 4 high-order address bus lines have been multiplexed with status signals.

AD0-AD15 : Address/Data bus. These are low order address bus. They are multiplexed with data. When AD lines are used to transmit memory address the symbol A is used instead of AD, for example A0-A15. When data are transmitted over AD lines the symbol D is used in place of AD, for example D0-D7, D8-D15 or D0-D15.

A16-A19 : High order address bus. These are multiplexed with status signals.

S2, S1, S0 : Status pins. These pins are active during T4, T1 and T2 states and is returned to passive state (1,1,1 during T3 or Tw (when ready is inactive). These are used by the 8288 bus controller for generating all the memory and I/O operation) access control signals. Any change in S2, S1, S0 during T4 indicates the beginning of a bus cycle.

S2

S1

S0

Characteristics

0

0

0

Interrupt acknowledge

0

0

1

Read I/O port

0

1

0

Write I/O port

0

1

1

Halt

1

0

0

Code access

1

0

1

Read memory

1

1

0

Write memory

1

1

1

Passive state

A16/S3, A17/S4, A18/S5, A19/S6 : The specified address lines are multiplexed with corresponding status signals.

A17/S4

A16/S3

Function

0

0

Extra segment access

0

1

Stack segment access

1

0

Code segment access

1

1

Data segment access

BHE’/S7 : Bus High Enable/Status. During T1 it is low. It is used to enable data onto the most significant half of data bus, D8-D15. 8-bit device connected to upper half of the data bus use BHE (Active Low) signal. It is multiplexed with status signal S7. S7 signal is available during T2, T3 and T4.

RD’: This is used for read operation. It is an output signal. It is active when low.

READY : This is the acknowledgement from the memory or slow device that they have completed the data transfer. The signal made available by the devices is synchronized by the 8284A clock generator to provide ready input to the microprocessor. The signal is active high(1).

INTR : Interrupt Request. This is triggered input. This is sampled during the last clock cycles of each instruction for determining the availability of the request. If any interrupt request is found pending, the processor enters the interrupt acknowledge cycle. This can be internally masked after resulting the interrupt enable flag. This signal is active high(1) and has been synchronized internally.

NMI : Non maskable interrupt. This is an edge triggered input which results in a type II interrupt. A subroutine is then vectored through an interrupt vector lookup table which is located in the system memory. NMI is non-maskable internally by software. A transition made from low(0) to high(1) initiates the interrupt at the end of the current instruction. This input has been synchronized internally.

INTA : Interrupt acknowledge. It is active low(0) during T2, T3 and Tw of each interrupt acknowledge cycle.

MN/MX’ : Minimum/Maximum. This pin signal indicates what mode the processor will operate in.

RQ’/GT1′, RQ’/GT0′ : Request/Grant. These pins are used by local bus masters used to force the microprocessor to release the local bus at the end of the microprocessor’s current bus cycle. Each of the pin is bi-directional. RQ’/GT0′ have higher priority than RQ’/GT1′.

LOCK’ : Its an active low pin. It indicates that other system bus masters have not been allowed to gain control of the system bus while LOCK’ is active low(0). The LOCK signal will be active until the completion of the next instruction.

TEST’ : This examined by a ‘WAIT’ instruction. If the TEST pin goes low(0), execution will continue, else the processor remains in an idle state. The input is internally synchronized during each of the clock cycle on leading edge of the clock.

CLK : Clock Input. The clock input provides the basic timing for processing operation and bus control activity. Its an asymmetric square wave with a 33% duty cycle.

RESET : This pin requires the microprocessor to terminate its present activity immediately. The signal must be active high(1) for at least four clock cycles.

Vcc : Power Supply( +5V D.C.)

GND : Ground

QS1,QS0 : Queue Status. These signals indicate the status of the internal 8086 instruction queue according to the table shown below

QS1

QS0

Status

0

0

No operation

0

1

First byte of op code from queue

1

0

Empty the queue

1

1

Subsequent byte from queue

DT/R : Data Transmit/Receive. This pin is required in minimum systems, that want to use an 8286 or 8287 data bus transceiver. The direction of data flow is controlled through the transceiver.

DEN : Data enable. This pin is provided as an output enable for the 8286/8287 in a minimum system which uses transceiver. DEN is active low(0) during each memory and input-output access and for INTA cycles.

HOLD/HOLDA : HOLD indicates that another master has been requesting a local bus .This is an active high(1). The microprocessor receiving the HOLD request will issue HLDA (high) as an acknowledgement in the middle of a T4 or T1 clock cycle.

ALE : Address Latch Enable. ALE is provided by the microprocessor to latch the address into the 8282 or 8283 address latch. It is an active high(1) pulse during T1 of any bus cycle. ALE signal is never floated, is always integer.

8085 microprocessor is an 8-bit microprocessor meaning that its data capacity is of 8 bits. Now mathematics is extremely limited with 8-bit number as its range is too small to carry out any bigger problem (range of 8-bit signed number is from -128 to +127). To increase the range we can combine the contents of two registers. (Range of 16-bit number is 65536). Any 16-bit number is called a word. Two important commands, ADC (Add with carry) and SBB

(Subtract with borrow) are required.

By 128 i guess you are referring to 128 kb of memory soo.. that isn't possible.

Because microprocessor 8085 is 8 bit

8085 microprocessor is an 8-bit microprocessor meaning that its data capacity is of 8 bits. Now mathematics is extremely limited with 8-bit number as its range is too small to carry out any bigger problem (range of 8-bit signed number is from -128 to +127). To increase the range we can combine the contents of two registers. (Range of 16-bit number is 65536). Any 16-bit number is called a word. Two important commands, ADC (Add with carry) and SBB

(Subtract with borrow) are required.

By 128 i guess you are referring to 128 kb of memory soo.. that isn't possible.

Because microprocessor 8085 is 8 bit memory address device and its total storage capacity is 2^8 = 256 Bites
and since its address is 16 bit it can access address from 0000000000000000 to 1111111111111111 which equals 2^16 which equals 65536bites = 64 kb

The bit size of a processor is normally defined by it ALU width, which equates to its main working register width. e.g.:

  • 8088 has 8 bit data bus, and 16 bit ALU so is a 16 bit CPU
  • 8086 is same as 8088 but has 16 bit data bus, also a 16 bit CPU

In both cases above the address bus is 20 bits.

  • 8080 and 8085 have 8 bit ALU and 8 bit data bus, address bus is 16 bit
  • many other 8 bit CPUs have 8 bit data and 16 bit address

Of course you can have the data bus wider than the ALU to boost memory performance. And a different address bus with to accommodate more memory, but the manipulation of memory addresses

The bit size of a processor is normally defined by it ALU width, which equates to its main working register width. e.g.:

  • 8088 has 8 bit data bus, and 16 bit ALU so is a 16 bit CPU
  • 8086 is same as 8088 but has 16 bit data bus, also a 16 bit CPU

In both cases above the address bus is 20 bits.

  • 8080 and 8085 have 8 bit ALU and 8 bit data bus, address bus is 16 bit
  • many other 8 bit CPUs have 8 bit data and 16 bit address

Of course you can have the data bus wider than the ALU to boost memory performance. And a different address bus with to accommodate more memory, but the manipulation of memory addresses get more complex and requires multiple steps; for 8086 these addresses were “far pointers”.